Magnetic amplifier circuit having a plurality of control inputs



Oct. 13, 1964 Filed Oct. 29, 1954 T. H. BONN MAGNETIC AMPLIFIER CIRCUITHAVING A PLURALITY OF CONTROL INPUTS 7 Sheets-Sheet l AB( Flux Dlflty)ATTORNEY Oct. 13, 1964 T. H. BONN MAGNETIC AMPLIFIER CIRCUIT HAVING APLURALITY oF coNIRoL INPuTs 7 Sheets-Sheet 2 Filed Oct. 29, 1954INVENTOR a m M .n.m WF b Il No flu L mm F 2- A THE ODORE H BONN ATTORNEYOct. 13, 1964 T. H. BoNN MAGNETIC AMPLIFIER CIRCUIT HAVING A PLURALITY0F' CONTROL INPUTS '7 Sheets-Sheet 3 Filed Oct. 29, 1954 PP-z e INVENTORTHEODORE H BONN BY ATTORNEY Oct. 13, 1964 Filed Oc'b. 29, 1954 T. H.BONN MAGNETIC AMPLIFIER CIRCUIT HAVING A PLURALITY OF CONTROL INPUTS 7Sheets-Sheet 4 |647 |30 Magnetic Store O1" :1

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BY wf# ATTORNEY THEODORE H. BONN BY wf# ATTORNEY Pimm Oct. 13, 1964 T.H. BONN 3,153,150

MAGNETIC AMPLIFIER CIRCUIT HAVING A PLURALITY oP CONTROL INPuTs FiledOct. 29. 1954 7 Sheets-Sheet 6 Fl .l7.

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THEODORE H. BONN ATTORNEY Oct. 13, 1964 T. H. BONN 3,153,150

MAGNETIC AMPLIFIER CIRCUIT HAVING A PLURALITY 0F CONTROL INPUTS FiledOct. 29, 1954 7 Sheets-Sheet 7 Input No.l

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Sum Output Carry Ouml INVENT OR THE ODORE H. BONN ATTORNEY United StatesPatent O 3,153,150 MAGNETIC AMPLIFIER CIRCUIT HAVING A rILURALI'IY 0FCONTRGL INPUTS Theodore iti-Bonn, Philadelphia, Pa., assigner to SperryRand Corporation, a corporation of Delaware Filed Get. 29, 1954, Ser.No. 465,624. 34 Claims. (Cl. 307-83) This invention relates to magneticamplifier circuits employing a plurality of control inputs andespecially such circuits in which a given number of the inputs must bein a predetermined condition in order to give a predetermined outputcondition. In addition, devices embodying the invention are peculiarlyadapted for use in computing or data translating systems.

Heretofore, gating and control circuits have employed diodes as the maincircuit components thereof, but diodes are likely to fail and it isdesirable to reduce the number of them required as far as possible. Itis an object to reduce the number of diodes required in circuits of thetype here involved and to replace some of the diodes with more reliablecontrol devices.

The principal object of the invention is to provide a gating circuitwhich responds only in event a predetermined number of input signalsoccur simultaneously to raise the device to a given threshold beforegiving an output, the principal parts of the device being magneticampliers so that it may be readily adapted for use in computer circuitsin which the remaining components are magnetic amplifiers.

Another object of the invention is to provide a gating system that islow in cost.

An additional object of the invention is to provide a gating system inwhich any given number of a plurality of control inputs may be energizedto produce a predetermined output.

Another object of the invention is to provide a gating circuit that isvery ecient and effective in operation.

Other and more detailed objects and advantages of the invention will beapparent as this description pro ceeds.

The present invention utilizes magnetic ampliers with their controlinputs so connected that a given number of control inputs must have apredetermined condition before the device produces a given outputsignal.

In some computer and data translating systems it is desirable that thecontrol inputs respond to appearance of pulses on input circuits, and inother computer circuits it is desirable that the device respond to theabsence of pulses on the input circuits. The present application showshow the gating circuits described may be used in either of these Ways.Moreover, it is sometimes desirable that in response to predeterminedinput conditions there be a pulse or a series of pulses at the output,whereas in other circuits it is desirable that the same predeterminedinput condition produce the absence of pulses at the output. Thisapplication teaches how either of these situations may be met.

Any of the hereinbelow described circuits may act as a magnetic gate ora magnetic butler, depending on its use in the computer' or datatranslating circuit. Consequently, to avoid repetition the devices willhereinafter be' referred to as magnetic gates. A gate is usually denedasa device wherein there is a signal output at the load only where thereare predetermined inputs at all of the signal sources of the device. Forexample, if all the signal sources had signals thereon occurringconcurrently and if this produced an output at the load, the devicewould be acting as a gate. The device would be acting as a butler if asignal (or the lack of ya signal) at any one of the signal inputsappears at one of the the computing system.

3,153,159 Patented Get. 13, 1964 ice output connections in complementedor non-complemented form, without appearing at any other signal input.By suitable connections to the circuit, the devices hereinalterdescribed may act as either a gate or a butter, and to avoid complexityof the description, will be referred to as gating systems.

Early'computing systems involved use of a large number of vacuum tubes.Later there have been developed computing systems involving numerousmagnetic amplillers of the general types hereinafter described inconjunction with FIGURES l and 12. A large number of these magneticampliiiers are interconnected with each other and with other circuitcomponents to constitute The present application discloses magneticgates that may be used in the computers that employ magnetic ampliers;but their main kapplication is in conjunction with a new and radicallyimproved computing or data translating system involving large numbers ofthese gates interconnected with each other (or with gates shown in mycopending applications hereinafter mentioned) and with other importantcomponents oi the whole system. The present application hasillustrations showing how the gates described therein may beinterconnected. An example of interconnected gates is a half-adderherein fully disclosed.

`ln the drawings:

FIGUREI is a schematic diagram of a magnetic amplilier circuit, which isnot part of the present invention but is employed in connection with theinvention.

FIGURE 2 is an idealized hysteresis loop for core material of themagnetic amplifiers.

FIGURE 3 illustrates the waveforms of the signal involved in FIGURE l.

FIGURE 4 is a schematic diagram of one of the gating circuits embodyingthe invention.

FlGURE 5 is a modified form of FIGURE 4.

FIGURE 6 is a partial view of another modied formy of FIGURE 4.

FIGURE 7 is a partial view of another modified form of yFGURE 4.

' FIGURE 8 is a waveform diagram for the pulses involved in FIGURES 5, 6and 7.

FlGURE 9 is aV schematic diagram of a gating system in which the outputhas a negative bias which is overcome when all or a plurality ofmagnetic amplicrs have signals at their inputs occurring concurrently.

FGURE 10 is a modied form of FIGURE 9 using pulse transformers in placeof magnetic ampliiiers.

FGURE ll is a schematic diagram of a modied form of FIGURE 4 utilizingpulse transformers in place of magnetic ampliiiers.

FGURE 12 is a schematic diagram of a non-complementing magnetic amplieruseful in explaining the circuit of FIGUREL 13.

FIGURE 13 isa block diagram of a halt-adder employing a gate. rthisfigure is not part of my invention but is included for purposes ofenabling me to point out how one of my novel gates may replace theconventional gate of this circuit.

FIGURE 14 is a waveform diagram of the device of FIGURE 15.

FIGURE 15 is partly a block and partly a schematic diagram of thehalf-adder of FIGURE 13 withrmy novel gate shown in place of theconventional gate.

FIGURE 16 is a waveform diagram of the device of FIGURE 15. i

FIGURE 17 is a system of threshold gates wherein signals in the outputswill show which combinations of signal sources are energized.

FIGURE 18 shows a regulating winding that may be employed in conjunctionwith any of the forms of the invention.

FIGURE 19 shows a half-adder involving threshold gates of the typesherein disclosed.

FIGURE is a timing diagram of the device of FIGURE 19.

FIGURE 21 shows an alternate form of half-adder involving thresholdgates.

In all forms of the magnetic ampliiiers hereinafter shown, the magneticcore may be made of a variety of materials among which are the varioustypes of ferrites and the various magnetic tapes, including Orthonik and4-79 Moly-Permalloy. These materials may have different heat treatmentsto give them different properties. The magnetic material employed in thecore should preferably, though not necessarily, have a substantiallyrectangular hysteresis loop (as shown in FIGURE 2). Cores of thischaracter are not well known in the art. In addition to the wide varietyof materials available, the core may be constructed in a number ofgeometries including both closed and open paths; for example,cup-shaped, strips and toroidal-shaped cores are possible. Those skilledin the art understand that when the core is operating on the horizontal(or substantially saturated) portions of the hysteresis loop, the coreis generally similar in operation to an air core in that the coil on thecore is of low impedance. On the other hand, when the core is operatingon the vertical (or unsaturated) portions of the hysteresis loop, theimpedance of the coil on the core will be high.

In order to furnish background information useful in connection withunderstanding the invention, a brief description of one type of magneticamplilier will now be given. For further details on this and other typesof magnetic ampliers, reference is made to the following twoapplications: Theodore Ii. Bonn and Robert D. Torrey, Serial No.462,858, tiled January 8, 1954, entitled Signal Translating Device; nowUS. Patent No. 3,071,694; John Presper Eckert, lr. and Theodore H. Bonn,Serial No. 382,186, tiled September 24, 1953, entitled SignalTranslating Device, now U.S. Patent No. 2,892,998. These applicationshave been assigned to the same assignee as the present application.

FIGURE l illustrates a complementing magnetic amplitler which isdescribed to provide background information. In that figure, the source16 of power pulses PP generates a train of equally spaced square wavepositive and negative going pulses having spaces therebetweensubstantially equal to the duration of the pulses. If it be assumed thatat the beginning of any given positive going pulse the core has residualmagnetism and ux density as represented by point Il of the hysteresisloop of FIGURE 2, the next positive power pulse will drive the core frompoint Il to point l2, which represents saturation. At the conclusion ofthe positive going power pulse the magnetizing force will return topoint lll. Successive pulses from power source 16 will iiow throughrectiiier 17, coil I8 and load i9, repeatedly driving the core frompoint l1 to point l2. During the interval in which the core is beingdriven from 1li to 12, the core is operating on a relatively saturatedportion thereof, whereby the impedance of coil IS is low. Hence,positive power pulses will tiow from source lo to load 19 withoutsubstantial impedance. If during the interval between the positiveexcursions of two of the power pulses, a pulse is produced at the inputsource Ztl, it may pass through coil 2li, resistor 22, source 16, toground. This will magnetize the core negatively driving it from pointIl. to point 13. At the conclusion of this negative pulse the core willreturn to point 14 where the magnetizing force is zero. The nextpositive power pulse from source 16 is just suiiicient to drive the corefrom point 14 to point 115. Since this is a relatively unsaturatedportion of the core, the coil 1S will have high impedance during thispulse and the current flow will be very low. At the conclusion of thatpositive pulse the magnetization will return to zero value lll. If nosignal appears on the d. input immediately following the last-namedpositive power pulse, the next positive power pulse will drive the coreto saturation at point 12 and will give a large output at the load I9.

Consequently, it is clear that the magnetic amplifier of FIGURE 1 willfeed large positive pulses to the load in response to each positivepulse from source 16, except that immediately after the receipt of anypulse on the input Ztl the next positive power pulse will be blocked.

In order to avoid appearance at the load 19 of the small so-called sneakcurrent which iiows during the period that a positive power pulse isdriving the core from point 114 to point 15, the negative source .'23,resistor 24 and rectifier Z5 may be employed. Suflicient current flowsthrough rectifier 25, resistor 24 and source 23 that the small sneakcurrent from coil 18 to output I9 is cancelled.

In one form of the device, coil I8 has twice the number of turns as coil21 and the source 16 has twice the electrical potential as the pulses oninput Ztl. The source i6 of positive power pulses, and the signal sourceZtl are so synchronized by any suitable means 26, that the signal pulsesalways occur during the spaces between positive power pulses. As shownin FIGURE 3, the signal pulses A and C, as do all other signal pulses,occur at times when the positive power pulses PP are at negative values.It follows from the foregoing description of FIGURE l that there will bea continuous train of power pulses in the output except during thoseintervals B and D which immediately follow the signal pulses A and C.

In some of the magnetic amplifiers hereinafter described, the means 23,24 and 25 for suppressing the sneak currents has been omitted from thedrawings and description, but could be added if desired.

The output of source 16 is an alternating current and goes negativeduring the space betweenk positive power pulses. rThe negative pulsemore than cancels any potential induced in coil I8 due to signalcurrents flowing through primary 21. As a result the negative excursionsof source 16 render the anode of rectifier 17 negative and cut oif thatrectifier.

The device of FIGURE l, just described, per se is not part of theinvention. It has been described primarily as background information andsecondarily since the circuit of FIGURE l is incorporated as a componentpart of some of the more complex circuits hereinafter described. Thedevice of FIGURE 4, now to be described embodies a basic and importantconcept and constitutes one form of the invention.

FIGURE 4 is a gating circuit in which simultaneous signals on all ofsources SS-l lto SS-4 inclusive are necessary in order for there to bean output across load S9. These signal sources would normally becomponents of a computer system such as for example output circuits of amagnetic store. The four signal sources SS- toy SS-4 normally supplytheir control pulses during the spaces between the positive pulses ofsource Sil. The details of the signal sources form no part of theinvention, in its broadest aspects, and therefore the sources are shownin block form in FIGURE 4. However, in connection with FIG- URE 5, thesignal sources are explained in more detail. The source till, of squarewave alternating current power pulses, feeds primary windings Sl, 82, 83and 84 which induce current in output windings 85, Se, 87 and d when thecores are operating on the vertical portions of their hysteresis loops.In the event any one of the cores is saturated at the beginning of anygiven positive power pulse, it will not induce substantial potential inits complementary output winding, and then the total potential appearingacross output coils to 38 inclusive will be insuicient to overcome thebias of battery @9a. In other words, battery 39a supplies such negativepotential that all (or a given number) of the output windings SS, 6, S7and SS must have maximum output potential in order to overcome bias ofthe battery 89a and cause a current to ilow in the load 89. Theselectively applied pulses from the signal sources SS-ii to SS--liinclusive tend to magnetize their respective cores negatively from pointll to point 13 on the hysteresis loop of FIGURE 2 during the period whenthe potential of source 80 goes negative. If all of them have produced asignal pulse simultaneously, the next positive power pulse from source8h will drive the four cores from point le to point ltf along thevertical portion of the hysteresis loop and maximum potential will beinduced in all tour output coils 8S to @d inclusive. The potential willthen be sufiicient to overcome the negative bias of the battery 39a andproduce current at the load S9. lf, however, there is no signal from oneof the signal sources, tor example SSS-i, the corecorresponding to thatsource will remain at point il on the hysteresis loop. The next powerpulse from source titl will then drive that core along the relativelysaturated portion lle-l2 ot its hysteresis loop inducing very littlepotential into the output winding 5. Hence, the total potential of thefour coils S5 to inclusive will be insuiiicient to overcome the bias ofthe battery @a and produce an output at the lor1 mi li desired, limitercircuits comprising elements this, Sdu, Seb, and 87h may be added to therespective stages in order to insure that none of them supply more thantheir proper share of the total potential to the circuit. Rectiiier hdais grounded, which means that the total potential of coils he, $7 andSBS can never exceed the bias oi the battery 39a. The lower end ot coiltiti is clamped to a negative potential E while the lower end of coil3'? is clamped to a negative potential 2E. The lower end of coil @d isconnected to the battery @ein which has a nega tive potential of 3E. Thelimiter circuits, therefore, prevent any one of the coils h5 to 38inclusive from supplying abnormally high potential to the'seriescircuit. Fo-

tential induced in coil 88, due to a positive pulse from source titiiiowing through coil h4 when the core is unsaturated, has a polaritythat opposes that of battery hat. Hence, if such potential induced incoil SS tends to exceed E volts the potential at the lower end of coil87 will tend to be more positive than the negative pole of battery 87a(whose potential is 2E) and current will ilow through rectifier 87h,battery 87a to ground thereby limiting the potential at the'upper end ofcoil tirs to -ZE volts. Simi larly, if the potential induced in coil 37tends to exceed E volts, current will liow through rectifier heb untilthe potential across coil 57 is limited to E volts.

Rectifier Sila prevents negative pulses from source titi from iiowingthrough coils tilt to $4. When the potential oi source @d goes negativeso that the anode of rectifier @da is negative, the rectiiier is cut orand will prevent any potentials that may be induced in coils il to 84',by reason oiE currents fed by sources SS-l to SSJi to coils Sla to @Ll-ofrom having a closed circuit through which current may i'low.

Rectiiiers hb, da c, @i3d and 8% preclude any potentials induced incoils 555 to inclusive, by reason ot currents ted by sources Sith?. toSS-4 to coils Sla to from having a closed circuit through which currentmay iow.

FiGURE 4 shows the signal sources SS-l to SSA inclusive with somegenerality for the reason that their exact details form. no part oi theinvention. The only important thing in connection with these signalsources is that they are parts ot a computer circuit which from time totime supply the necessary control pulses, timed to appear during thespaces between the positive pulses of source 8).

` FlGURE 5 shows in a little more detail one way oisectu'ing thenecessary timing. in FlGURE 5, there are two sources or" power pulsesPP-l and PP-Z. The pulses of source Pil-2 go negative when the sourcesof Pil-l go positive, all as shown in FIGURE 8, therefore source PP-Z iscapable of supplying control pulses during the spaces between positivepulses of source PP-Ii. Signal sources (which in this case are Switches)S841 to SS-i inclusive are respectively in series with coils Sla toSiria inelusive. Hence, in event any one of these switches is closed,its complementary coil, for example coil 81a in the case of switch SS1,is energized during the spaces between positive power pulses of source80. It is understood that in a computer circuit the switches SS-l toSS-Lt inclusive could be any component of the computer circuit which ineffect closes the circuit to allow pulses from source PP-Z to iiow tocoil @la and the switches are shown in their mos-t elementary form onlyfor purposes of illustration.

Another modiiication of FIGURE 4 is also shown in FGURE 5, namely acomplementing magnetic amplifier of the type shown in FIGURE 1 isconnected in series with the load S9. This is optional and may beemployed in the event it is desired to reverse the output at the load.As stated in connection with FIGURE 4, simultaneous signals on all ofsignal sources SS-l to SS-4 inclusive are necessary in order for thereto be an output across load 89. in FIGURE 5, if the complementingmagnetic amplifier is used in the load circuit, the closing of all theswitches SS-l to SS-4 inclusive would cause a pulse to appear at theinput coil 2li of the complementing magnetic amplifier, but inasmuch asa` complementing magnetic amplifier produces no output during a timeperiod immediately following an input pulse, it is apparent that therewill be no output at load S9 of FEGURE 5 in event all tour switches SS-lto SS-4 inclusive of FIGURE 5 are closed.

Likewise, in event one (or more) of switches SS-l to SSJS of FIGURE 4 isopen, there will be no output at the load 9. However, in connection withFIGURE 5, this same situation would produce an output pulse at the load89. This follows from the fact that if any one of the four switches wasopen, there would be no input at coil Ztl of the complementing magneticamplier and therefore the magnetic ampliiier would produce an output inresponse to the next pulse from source PP-Z. v

it is noted in connection with FIGURE 5, that the cornplementingmagnetic amplifier requires that its source of power pulses be out ofphase with any signal pulses fed to the input coil 2l. This isaccomplished by connecting the power winding 13 to the source PP-2 whichis out of phase with the pulses from the source PP-l, the latter sourcecontrolling the flow of pulses to the input coil 21.

FIGURE 6 shows a way oi reversing the effect of the input pulses to theseveral magnetic ampliiiers of FlG- URE 4. A complementing magneticamplifier of the type shown in FIGURE l may be placed between the switchSS-li and the coil rila. lt is required7 in connection with thecomplementing magnetic arnplilier of FiGURE l that the input signalthereto be out of phase with the power pulse fed thereto. In order toaccomplish this, two generators of power pulses Pil-1 and lP-Z are usedin FlG- URE 6 and have the relative waveform shown in FG- URE 8. SwitchS84 controls the flow or pulses TPE-1 to the input oi the complementingmagnetic ampliiier, and source PP-Z controls the flow of power pulses tothe coil i3 of the magnetic amplifier. Therefore, the output pulses oithe complementing magnetic amplifier are in phase with the pulses ofsource PP-Z and are fed to coil @la and are therefore out of phase withthe pulses from source PEP-l flowing through coil 81. It is understoodthatVFlGURE 6 is only a partial showing and that in a complete systemthere would he complementing magnetic amplifiers in series with ask manyof the switches SS-l to SES-4- inclusive (of FGURES 4 and 5 as desired.

A still further modification is shown in FGURE 7 which is likewise apartial view of a complete device such as is shown in FIGURES 4 and 5.in this case, resistor 'itl and battery '7l are placed across the coil81a and tend to pass a current through that coil which will reset thecore (from point il to 3.3 on the hysteresis loop of FGURE 2) in eventswitch SS-l is open. In event switch SS-l is closed, the pulses fromsource PP2 will cancel the eiiect of battery '71 and thereby preventre-r setting the core. Hence7 the effect of the switch S34 on the coilSla is reversed in FlGURE 7 as compared to the circuit of FlGURE 5. Theresetting circuit lil-7l, shown in conjunction with switch SS-ll, couldequally Well be used in connection with switches SS-Z to {3S-fiinclusive of FlGURES 4 and 5.

In connection with the remaining figures described in this application,the signal sources are shown conventionally in block form. lt isunderstood that this is merely an expedient of simplicity and thatwherever a signal source is shown it may well be any element ot acomputer circuit which provides the necessary pulses at the correct timeand in particular it may involve any one or more of the principlestaught in connection with FlG- URES 5, 6 and 7. That is, it may e aswitching device which controls the flow of pulses from a second pulsesource FEP-2, as shown in FlGURE 5. Alternatively it may comprise amagnetic amplifier as shown in FGUR 6, or it may have a resettingcircuit Til-7l in combination with the second source of pulses, as shownin lalG- URE 7.

FlGURE 9 is a gating circuit in which all or a predetermined number ofsignal sources SS-l to SS-E inclusive rnust be in the inoperative state(no pulse output) during the period immediately preceding a givenpositive power pulse from source dll, in order for there to be currentin the load lle. rEhe source 9d of alternating voltage (having goodvoltage regulation) tends to pass current through the coils @1, 12 andin parallel, to the load 9d. The three ampliiiers operate insubstantially the same way as was previously described in connectionwith FlGURE l, and they operate on the saturated portions of theirhysteresis loop only in the event a given positive power pulse fromsource was not preceded by a signal pulse. A biasing battery 99a passescurrent through resistor 99h and rectifier ElJc to ground. The resistors96, 97, 93 and 9%, have such resistance values that all three (or apredetermined number) of windings 9i, l2 and 93 must be conductingbefore the power pulses from source 9@ are sulicient to overcome thenegative bias of the battery 99a and produce a current at the load. Inother words, it all three secondaries 91, @Z and 93 concurrently havelow impedance, the current llowing through the three branch pathsBil-95, 23? and @fi-@3 will be sutlicient to raise the potential at theupper terminal ot the load to a positive value notwithstanding thenegative potential of battery 91 Rcctilier 99e will therefore be cutoli, and each positive pulse from source @il will divide, part of ittlowing through resistor 9% to battery 99a to ground and the remainderthrough the load 94 to ground.

The signal sources SS-l to SS-F of FlGURE 9, as in all other ligures,normally produce control pulses only while the potential of source Si@is negative. The fact that source goes negative prevents any positivepotentials that may be induced in coils 91, 92 and 93 due to signals fedto the three input windings from the three signal sources from producingcurrents. in the load circuits. The lower ends of resistors llo, 97 andg3 are clamped. to a given positive potential by battery 95 andrectiliers 95a, 9511 and 95e. The clamping prevents any one of the threestages from supplying more than its proper share of the load current.The rectiers lloc, 97a and 9&1 enable the device to have both a powerand an energy gain. That is, more power and energy will appear at theload 9d than is required of signal sources SS-i to S54) inclusive. Thisresult is accomplished since the rectiiiers preclude reverse flow ofcurrents in power windings 9i, 92 and 93 and enable the generator ofpower pulses 9@ to supply a large flow of current through coils 9i, 9?,and 93 when they have low impedance and the polarity of the generatorSie is positive.

FGURE lil is a modified form of FlGURE 9 employing pulse transformersinstead of magnetic ampliiers. No source of power pulses is employed inthis form of the device, as the powerV to the load is supplied by thesignal sources through the several pulse transformers. The 'three signalsources SS-i to SiS-T; inclusive respectively energize the primaries ofthe three pulse transformers ith?, lltll and ltlZ, the secondaries ofwhich produce substantially square wave outputs. The current from thesccondaries of the transformers ltlil, lill and to2 inclusiverespectively low through rectiiers 03, and ltlS and thence respectivelythrough resistors ltllla, lilla and litio to the load. A negative biascurrent is placed in the output circuit throuffh resistor lbla. .it isonly when all or a given predetermined number of the signal sources SS-lto SS-3 inclusive are energized that a sufiicient potential is developedto overcome the negative bias current and to give a positive outputpulse at the load. This is accomplished by properly proportie-ningresistors Tintin, lla, lltlZ/z. and E Qla. A limiter is associated withthe secondary of each transformer in order to prevent that particulartransformer from delivering in excess of its proportionate share of thenecessary current. This limiting is accomplished by rectiers lib-tf,lil? and ftllti inV combination with battery H in the manner abovedescribed.

ll is a schematic diagram of a modified form of FUURE i in which pulsetransformers are substituted for magnetic amplifiers. A sufficientnegative bias lilla is placed in the load circuit so that all four otthe puise transformers to inclusive msut be concurrently energized inorder to overcome the bias and cause current to flow through rectifieril@ to the load. ln order to prevent the secondary il' lfrom deliveringmore than its proportionate share of the total potential, limiterlila-Mrz is employed. lt is noted that source ot bias has 3E volts incontrast with 2E volts for source ltia. Likewise, limiter lilla-m2oprevents the potential, developed in coils llo and lli taken together,from raising the lower end of coil lilla above -E volts. rihe rectifierlill) prevents the three secondari/es ll to M7 inclusive from raisingthe lower end of coil lll@ above ground potential. Hence, unless allfour signal sources SS-ll to SS-/l inclusive are concurrently energized,there will be no flow of current to the load. But if all four of thesesignal sources are simultaneously energized the combined potentialsdeveloped in coils to M7 inclusive will overcome the bias of batter iz-nand current will flow to the load. As in the case of other iigures,suitable means 26 may be employed whereby sources ESS-ll to SS4 emitpulses only at predetermined time intervals.

ln order to illustrate a practical application of the invention, l willillustrate the same as replacing a conventional gate in a modern type ofhalf-adder. rlhe halfadder which l choose to mention in connection withthis explanation is the one which is subject matter of copendingapplication of Joseph D. Rutledge, Serial No. 424,035 tiled April i9,1954, issued September 17, 1957 as Patent No. 2,806,548, entitledl-lali-Adder for Computing Circuits, assigned to the same assignee asthe present case.

ln orde-r to understand the half-adder circuit of Rutledge, it is firstdesirable to explain the operation of a non-complementing magneticamplifier. A typical noncomplementing magnetic ampliiier is illustratedin FIG- URE l2 and employs a source l2@ producing an uninterrupted trainof power pulses which are equally spaced and generally the spacesbetween the pulses are equal to the duration of the pulses. The signalsource l27 produces from time to time the control signals and by reasonot any suitable means SS, these control signals are always synchronizedto appear during spaces between the power pulses. When the power pulsesfrom source lZtl are positive they pass through rectifier lfll, coilT122, re sistor l27 to negative pole i213- which is below groundpotential. lf we assume that at the start of the irst pulse the core wasat point l/lon its hysteresis loop (see FlG- URE 1), it will be drivento point 15. At the conclusion of the first pulse, current will flow inthe following circuit: from ground to rectifier 126, coil 122, resistor123, to negative pole 125i. This is a current liow through coil 122 inthe opposite direction from that of the irst pulse and drives the corenegatively from point 11 to point 13. At the conclusion of this reversepulse, the second power pulse will drive the core positively from point13 through point 1li to point 15, and from thence it will go to 11,after the conclusion of the second pulse. The next action will beanother tiow of current in the following circuit: from ground, rectifier126, coil 122, resistor 123, to negative pole 12d.

Hence, the magnetization of the core will repeatedly traverse thehysteresis loop and the majority of the time the core will be operatingon unsaturated portions of the hysteresis loop, consequently there willhe substantially no output. lf, however', an input signal is received incoil 125, at a time when the core is at point 11, the reverse current(in circuit: ground 126-122-123-1241) will not drive the core negativelyto point 13 as usual. ln such situation, there will be two oppositemagnetizing forces on the core. On the one hand, there will be a flow ofcurrent in the circuit: ground to rectiierld, coil 12,2, resistor 123,to negative pole 12d, tending to apply a negative magnetizing force tothe core. There will be an additional input current in coil 12S tendingto apply a positive magnetizing force to the core. These two magnetizingforces will cancel each other and the core will remain at point 11 onthe hysteresis loop. Consequently, the next powery pulse will passthrough rectiier 121 and coil 122 to the output. lt will drive the corefrom point 11 to point 12 on the hysteresis loop. The core issubstantially saturated throughout this entire pc` riod, and therefore alarge pulse output will appear. The operation of the noncomplementingamplifier may be summarized by stating that the currents will drive thecore around the hysteresis loop without substantial saturation andtherefore without any substantial pulse output until there is a currentflow through coil 125. This will interrupt the alternatingmagnetizations ot the core, allowing the next power pulse to saturatethe core and give a large output.

FIGURES 13 and 14 illustrate the hali-adder invented by Rutledge asaforesaid, and wherever in the following description of those figuresreference is made to a complementing magnetic ampliier, it is understoodthat such amplifier may be of the type shown in FGURE l of thisapplication; and wherever reference is made to a noncomplementingmagnetic amplilier it is understood that the amplifier of FIGURE l2 maybe used.

Referring now to the hiock diagram of FIGURE 13, it is noted that thecomplementing magnetic amplifier 135' passes a continuous series ofpower pulses Pil-1 through butler 136 to the sum output 1.37, in theahsence of a signal on wire 134. The two binary signals to be added,which may have the waveforms shown in FIGURE 14, are fed onto terminals13) and 131 from a magnetic store or other element. if there is a signalon either one of these inputs 130 or 131, the next succeeding powerpulse to amplilier 1.35 produces no out put. This is clearly illustratedin FIGURE 14 where it is noted that power pulses PP-l occur at 140, 1611and 1412 respectively, producing sum output pulses at 143, 144 and 145.However7 when input pulse 146 occurs at input 139, the next succeedingpower pulse 147 does not llow to the sum output 137. lil/hen inputpulses occur simultaneously at input terminals 1341 and 131, the diodegate 13S becomes conducting and triggers the non-complementing magneticampliiier 139 so that the latter allows the next power pulse `to iiow tothe carry output 13% and the sum output 137. This is clearly illustratedin FIGURE 14 which shows the inputs 130 and 131 as having received inputpulses 148 and 149. These cause a pulse 150 at the sum output 137 and apulse 151 at the carry output 13911.

it follows from the foregoing that when there is no signal on eitherinput, there will be no signal at the carry output 13% and there will hea continuous series of power pulses at the sum output 137. When there isa pulse on just one of the input terminals 13d and 1111, there will be apulse on wire 134 which will interrupt the next power pulse fromamplilier 135 and give an indication in the sum output 137 by theabsence of a pulse. When there are simultaneous input pulses on bothIterminals 131i and 1.31, the amplifier 139 allows the next power pulseto pass to the carry output 1391;, indicating a carry digit and also topass to the sum" output 1217 indicating the lack of a sum.

The gate 131i of FGURE 13 is the important element so far as thepresentapplication is concerned, inasmuch as the present applicationdiscloses a novel gate which may be substituted for the gate 138 ofFIGURE 13. 1n FGURE 13 the gate 133 produces an output pulse only whenthere are concurrent input pulses on input wires Sil and 131. ln otherWords, in event there are simultaneous input pulses on wires 151i and131, the gate will supply an input pulse to amplifier 139. 1n theaforesaid Rutledge application, the gate 133 is the con- Y ventionaldiode gate.

FIGURE l5 is a semi-schematic diagram of the circuit of FIGURE 13 withthe gate of the present invention substituted for the gate 13d of FlGUlE13.

ln connection with FIGURE l5, those parts which are identical withcorresponding parts of FIGURE 13 bear like reference numbers. There aretwo generators of power pulses Pil-1 and PP-Z which have the waveformsshown in FlGURE 16. lt is to be noted that the sources supply constantpotential pulses to the amplitiers 135, and 162, and supply constantcurrent pulses to windings 173 and 171i.

ln FIGURE l5 the parts 170 to 173 inclusive repre-y sent a gatingcircuit built according to the teachings of FlGURE s and which replacesthe gate 132B of FlG- Ull 13. The ,gating circuit of FlGURE l5 hassecoudmy coils 17d and 171 in series with battery 172 and so arrangedthat if either of the secondaries or 171 alone has a maximum potentialinduced therein, that potential will he counteracted by the negativebias of the battery 172 and no current will liow through rectifier 176to the input 163 of the non-complementing magnetic amplifier 139. lnevent maximum potential is concurrently induced in beth of coils 17@ and171, the negative bias of the battery 172 is more than overcome and apositive pulse flows through rectifier 176 to the input 163 of thenon-complementing magnetic amplitier 139. Source of power pulses PP-lltends to pass current through coils 173 and 171i to ground. Input coils177 yand 178 are respectively energized by the input pulses 130 and 131from the magnetic store orother source of pulses As shown in FlGURE 16,pulses from the magnetic store or other source always occur 0n inputs13@ and 131 during the spaces between pulses of source PP-l, in otherwords, during the periods of positive pulses from source lP-Z. ln eventthere are no pulses on inputs 13) and 131 neither of the coils 177 or17S will reset its respective core and the power pulses from source PP-lflowing through the coils 175 and 174, will saturate the cores and therewill be very small potentials induced in coils 17? and 171. The negativebias of battery 172 will therefore not be overcome and there will be nopulse liowing to the input 163. In event only one of the inputs 130er131 is energized, the result will he the same, although the reason whyis slightly different. Assume that a pulse exists on wire 134i without apulse on wire 131. rl`he pulse on input 131i lowing through thecoil 177will reset the upper cores whereas the lower core will not he reset.Hence, the next pulse from source PP-l flowing through coils 173 and 174will drive the upper core along an unsaturated portion and inducemaximum potential in coil 170, while the current flowing through coil174 will saturate the lower core and induce 3,1 l l practically nopotential in the coil ll. Since maximum potential across coil llil isinsufficient to overcome the negative bias of battery ilZ, there will beno i'low of current to the input i163. On the other hand, if inputsignals appear simultaneously on inputs i3@ and llSl, both cores will bereset during the spaces between pulses of source PP-l and the next pulsefrom that source will ilow .through coils 173 and 174, driving bothcores along unsaturated portions and inducing maximum potentials incoils l'il and ll71, thus overcoming the negative bias of battery l72and supplying a pulse to the input 3h53.

It is noted that by inserting the magnetic gate of the present inventionfor the diode gate of Rutledge, the output to2 from the gate has beendisplaced by one time period with respect to the input- Therefore, inorder to prevent this from having an adverse effect upon the haliaddercircuit, it is necessary to delay the pulses that would normally appear'at the input of complementing magnetic amplilier 135 by one time period,and consequently, the non-complementing magnetic ampliiler loi. isplaced in series with the input l5?. of the complementing magneticamplifier E35. lt is clear from the foregoing description that thepulses received on wires 152 and lie are identical with the pulsesreceived at the inputs of ampliliers 135 and l of FIGURE 13, the onlydifference being that the pulses in FlGUli l5 are displaced from thoseof FlGURE 13 by one time space.

A second source of power pulses FP-Z is therefore employed connectionwith ainpliiers i3d and i) of FlGURE l5 so as to properly amplify thedelayed pulses which are received by those ampliiiers and as a result,the outputs on wires 13.37 and of FlGURE, 15 are identical with those onsimilar wires of FlGURE i3 except displaced by one time period.

The waveform diagram of FlGUlll 16 clearly shows the relations of pulsesin the device of FIGURE 15, and shows that the mode ot operation otFlGURE 15 is substantially identical with that of FlGURE 13 except ashereinabove pointed out. ln order to visualize the sum output of FlGUREl5, it is merely necessary to add together the pulse appearing on wire1.53 of FlGUll 16 with those appearing on wire i163.

As shown in FlGURE l5, tile source of pulses leal may be a magneticstore or any other source of controlled pulses. It it is a magneticstore, it may be of any suitable type, and would have the several binarynumbers stored therein in such a way that when the apparatus is inoperation the binary signals emerging therefrom will be in the form ofpulses appearing during the spaces between the pulses of source PF4.This is clearly shown in FIGURE 1 6 where all of the pulses on inputsi3@ and ll appear during the spaces between pulses of source PP-l.

ln event the device lr6-t is a mechanism other than a magnetic store, sothat it is a trigger device which controls the ilow or pulses to wireslh and 33t, it would normally be fed with pulses from source PP-Z sincethe pulses of this source appear during the gaps between the pulses osource PP-l. lt is understood that in connection with a completecomputing system embodying magnetic amplifiers, the two sources oi powerpulses PP-l, and HL2 would normally be present and would supply pulsesto a large number of diiterent magnetic devices throughout the entirecomputer' system, consequently each element, such as "tell, which mightfeed the input to the new gating system would normally be fed with powerpulses from one of the two sources PP-ll or Pil-2 contained in theoverall system. ln adapting the gate to such a situation, it is merelynecessary for the gate to be connected to the source of power pulsesother than the one which supplies power pulses to the control ele nentof which 164- is an example.

While the invention has been described broadly in connection withiigures such as FIGURE 4, it is understood that it has a wide variety ofdetailed applications in computer circuits of which SiS- STS-3, and fourloads i7?) to 175 inclu-- sive. The energizations of the loads willindicate which combinations of signal sources a e concurrentlyenergized. There are three l aguetic c res l'ltl, 1.7i and 172 of typesheretofore mentioned, having power windings ource ot alternating currentpower pulses Pl. A rectifier is normally included in the circuit tolimit the llow of current to one direction only.

The signal sources SS-l, S55-2 and SS-S respectively control coilsl'ilb, l'llb and llZb, and a signal from one or" the sources tends torevert its complementary core to point ift on the hysteresis loop ofFIGURE 2 so the next power pulse from source PP will drive the corealong the unsaturated portion thereof, lll-l5, and thus induce potent..l in the secondary coils which are located on the cores. rEhe coresrespectively have coils l'ilc, llc an connected in series with eachother, as well as in series with load 1'73, rectier 173:1 and battery173i?. Eattery lifvb normally places such a large negative potential onthe anode of rectifier 173e that no current can flow in the circuitunless potential is induced in all three of coils ltlc, l'/lc and i726.ln other words, the potential of battery i735 is slightly greater thanthe potential normally expected from the two secondaries l/lc and 172Cif energized together in the absence of an induction of potential in thecoil .lllc ln event only two of the three coils l7tlc to lZc receiveinduced potential, there will be no ilow of current in the load 173 butthat load will receive a current in event all three coils l'llc to i726have induced potentials therein.

load E74 is in series with rectifier $7411 and battery lil/lb. Thelatter normally biases tue anode of rectifier li'fla negatively so thatin event potentials are induced in one only oi coils 17M and l'id, thepotential of the battery will not be overcome and no current will ilowin he load lil-4; however, if potential is induced in both coils Jildand Ilrz' simultaneously, the potential induced in the two coils will betwice that of battery 1Mb and will tend to cause ilow of current in theopposite direction from that of battery llb and therefore current willHow in the load Load 17S is in series with rectifier 175:1 and batterylb. The latter normally biases the anode of rectilier 175s negatively sothat no current will ilow in the load unti the potential built up incoils ltle and lle is greater than that of the battery lb and in theopposite direction from the potential of the latter. When only o -e ofcoils llle and i712@ is energized, the potential of the battery 175,5 isnot overcome; however, when both coils 17de and "i712 receive inducedpotential the potential of battery le is overcome and current flows inthe load i755.

The load No has rectifier loa and battery 17o!) in series with it. Thelatter biases the anode of rectilier fida negatively so that no currentflows in the load circuit until the potential of the battery isovercome. lf only one of the secondary coils ltlf or 17E-f is energized,the potential of the battery lob will not be overcome and no currentwill ilow in the load 17o; however, if potential is induced in both ofthe coils lilf and 1721, current will flow to the load lilo.

When the load i373 is energized, that is an indication that all threesignal sources were energized concurrently.

, 13 When load 174i is energized, it is an indication that signalsources Sti-1 and SS- were energized concurrently. When load 175 isenergized, it is an indication that signal sources SS-l and SS-Z wereenergized concurrently. When load 176 is energized, it is an indicationthat signal sourcesSS- and SS-S were energized concurrently.

FIGURE 1S illustrates a modification of llGURE 17 which may be includedin the device of FIGURE 17 if desired. In order to limit the potentialinduced in the coils on the cores so that irrespective of the operationof the device any one coil will always produce a given potential whenthe core is in the high impedance state, the coil 18? in series with asource 151 and a rectilier 1S?, i Lay be employed. When the core is inthe high impedance state and a power pulse ilows through 19241, the fluxmay readily change until the potential induced in coil 18h exceeds andopposes that of battery 181. When the induced potential exceeds that ofthe battery, rectifier liti?. conducts and constitutes a low impedancepath around the coil 1bn which tends to prevent further change of uxthrough the core. Hence, the rate ol' change of the linx is 'limited andconsequently the potentials induced in coils 170C, ldd and 176e arelikewise limited. The improvement constituting parts 181) to SZ may beapplied to any of the cores in any of the figures.

As hereinbefore stated, the primary object of the invention is toprovide a new gating system component which may be connected with othersuch components and with other components such as magnetic stores) toform a complete computing or data translating system. Flf URE i9 is oneillustration ot how the coils of a threshold gating system may beinterconnected to form a half-adder.

FIGURE 19 illustrates two inputs 19d and 191 for receiving the two inputsignals to be added. As is known in connection with halhadders operatingon the binary system, when neither input is energized at a given signaltime period there should be no signal at the sum output 199. It eitherinput 19d or 191 is alone energized, there should be a. signal at thesum output 199 but no signal at the carry output 2dr?. ln event bothinputs 19d and 191 are energized concurrently, there should be no signalat the sum output 199 and a signal at carry output Zilli. The inputsignals received at inputs 19h and 191 are usually serial trains ofpulses so spaced that they represent binary numbers. The signals on thetwo inputs are properly synchronized so that they constitute two numbersto be added. v

The magnetic cores 192 `and 193 are the same as those described inconjunction with the other figures of this application. input 191icontrols coil 192e and input 191 controls coil 193g. Alternating currentpower pulses are fed from source PP through coils 192i? and 19315. Thecarry output circuit includes coils 192e and 193e in series with battery194i, rectifiers 195 and 196 and the carry output terminal 2199.Rectiiier 139 prevents the potential induced in coil 193e from exceedingE volts.

Coils 192e, 192:1, 193C and 19361 -in conjunction with rectier 197' and19? control the sum output 199.

On positive halves of the cycle, the source PP energizes coils 19215 and193i tending to drive the cores from point 14 to point 15 on thehysteresis loop of FlGURE 2. lr there are no inputs at 19@ kand 191, thecores are not reverted to point 1dduring the spaces between power pulsesand accordingly the next power pulse from source PP saturates the cores192. and 193. Since the cores are open ating on saturated portionsthereof, the iiux change will be small and no potentials vwill beinduced in coils 192C, 192d, 192e, 193C, 19T-d and 193e. lt follows thatthere will be no outputs at either suni output 199 or carry output Zoli.This condition is illustrated in FlGURE 2G prior to the time that pulsearrived at input 19t?. The input pulses always arrive during signal timeperiods, that is during the intervals when source PP is going negative.As shown in FlGURE 20, when pulse Zilli arrives at input 19t), it flowsthrough coil 192e and reverts the core 192 to point 14 so that thenextpositive power pulse 202 from source PP will drive the core alongthe unsaturated portion thereof from point 14 to point 15 and thusinduce in the coi-lsf192c, 1920, and 192e a potential of E volts. Sincecore 19.1 was not reverted by a signal pulse, no potentials are inducedin coils 193e, 1934i and 193e by the positive pulse 292. As stated, therapid flux change in core 192 induced a potential in coil 192C andcurrent will therefore ilow through rectiiier 197 to sum output 199. Thecornplete circuit through which this current flows is as follows: coil192e, rectifier 197, output 1.99, ground, coil 193C, back to coil 192C.Hence, there will be a sum output at 199. There will be no carry outputat 209, for although a-potential is induced in coil 192e, it isapproximately equal and opposite to the potential of battery 194 andtherefore these two potentials cancel.

As shown in FGURE 20, the apparatus has no further input pulses until ata later time pulses 294 and 205 appear concurrently on inputs and 191during a signal time period. These pulses respectively dow through coils192:1 and 193aand revert both cores 192 and 19? sokthat tine nextpositive pulse 2.06 from power pulse source PP induces potential in allof the secondary coilson both `of the cores. Hence there will bepotentials of E volts induced in both coils'192e and 193e. The potentialinduced in coil 193e will be equal and opposite to that of battery 194and hence the cathode of rectier 195 is essentially at ground potential.The potential induced in coil 192e will raise the anode of rectifier1963 to -l-E volts and consequently that potential will appear at carryoutput 2% in the forni of pulse 267 (see FIGURE 20). There will be nooutput at the sum `output 199 under these circun1- stances, since coils192e and 193e are wound in opposite directions so that the potentialsthey produce are equal and opposite and cancel each other. Likewise,coils 192d and 193e! are wound in opposite directions and theirpotentials cancel each other. There are no further input pulses untilpulse 298 (or FIGURE 20) appears at input 191. That pulse reverts thecore 193 during a period when core 192 is not reverted. Hence, the nextpositive power pulse 209 from source PP drives core 192 along asaturated portion thereof and core 193 along an unsaturated portionthereof so that potentials are induced in coils 193C, 193d and 19.9@ butno potentials are induced in coils 192C, 192:1 and 192e. The potentialin coil 193d will cause a ilow of culrent as follows: coil 193d, coil192d (which has low impedance) rectier 198, sum output 199, ground, backto coil 19Std. Hence there is a sum output at 199. There is no carryoutput at Zilli since only one of the two coils 192e and 193e has apotential induced in it. The potential induced in coil 193e is equal andopposite to that of battery 194, hence the rectitier`195 is at groundpotential. There is no potential induced in coil 192e and hence rectier196 remains at ground potential as does carry out put 299.

The coil 139, battery 181 and rectier 182 control the iux change in thecore 192 and prevent any of the coils 192C 1925i and 192e fromgenerating more than E volts, all as explained in connection with FIGURE18. It is unnecessary to have all three of these elements on core 193 inaddition to the elements already described, since some of the elementsassociated with core 193 may serve a dual purpose. Battery 194 may servethe purpose already ascribed to it and in addition serve a purposeequivalent to battery 181. Therefore, it is merely necessary to addrectifier 139 in order to control the potentials induced in coils on thelower core 193. It is noted that the cornbination of coil 193e, battery194, rectifier 195 and rectilier 189 will provide the limiting functiondescribed in connection with parts 180, 181 and 182. In event thepotential induced in coil 193e should exceed E volts, current would liowthrough rectifier 189 and limit the rate of change of the flux in core193 so that the potentials nduced in the three secondary coils of core193 will all be E volts.

FIGURE 21 is a description of a half-adder similar in all respects tothat of FIGURE 19 except in regard to the voltage limiting functions onthe cores. The corresponding parts on FIGURE 19 and 21 are designated bysimilar reference numbers. For purposes of the present discussion,rectifier 212 may be omitted and the apparatus will first be describedwithout it and later with it.

Rectifier 2li) in combination with a source of potential 211 which has Evolts above ground will provide the necessary limiting function. lnevent core 192 is operating on an unsaturated portion while core 1% issaturated, it is of course merely necessary to limit the flux change incore 192. This will be done since coil 192C will have a potentialinduced in it. This potential is contributed solely by the flux changein core 192 and therefore by limiting the potential on output 199, therate of flux change in core 92 is limited. Likewise, in the case whereinput lll is the only one that is energized so that core E93 is the onlyone operating on an unsaturated portion of its hysteresis loop, the onlypotential contributed to the sum output 199 will be by virtue of coil@3d and by limiting the potential at output 199, through the rectifier21d and the positive source 2li, the rate of flux change in core 93 willbe limited and the potential induced in all of coils 193C, 1936i and @Sewill be actually limited to E volts. lt is normally unnecessary to limitthe potential at the carry output and consequently rectified 212 may beomitted. lf inputs 19t) and 191 are both energized and coils 192e and@Se contribute more than E volts each, it will merely mean that thecarry output will rise above E volts but no harm will be done in thisregard. lf, however, it is desired to limit the carry output potentialto E volts, rectifier 212 may be added. This will tend to control theduration of the carry output pulses and have other obvious rninoradvantages.

I claim to have invented:

1. In an electrical circuit; a plurality of sources of signal pulses;and means responsive to signal pulses from a plurality of said sourcesfor producing including at least one complementary source an outputpulse comprising a core for each source, said core being substantiallysaturated at remanence, means for altering the magnetization of eachcore in response to a signal from the complementary source, potentialdeveloping means including a second and third winding on each core fordeveloping a potential in said third winding in response to energizationof said second winding following magnetization of the core, in responseto said signal, and output means interconnecting the third windings forproducing an output condition in response to development of givenpotentials therein by a given plurality of said potential developingmeans, said output means including a potential source of fixed biasconnected in series with said third windings which opposes thepotentials of each of said plurality of potential developing means andprecludes the potentials of the potential developing means fromproducing said output condition until said given plurality of potentialdeveloping means are concurrently energized to produce a potential thatovercomes that of said xed bias.

2. An electrical circuit comprising a plurality of sources of signalpulses including at least one complementary source, a core for eachsource, said core having a substantially rectangular hysteresis loop, afirst Winding on each core connected to its complementary source,potential developing means associated with each core for developing apotential depending on the magnetization of the core including a secondand third winding on the core, means for concurrently energizing each ofsaid second windings and means for giving a predetermined output inresponse to development of given potentials in a given plurality of saidthird windings in response to energization of said second windings, saidlast-named means including a potential source of fixed bias connected inseries with said third windings to oppose the ld potentials developed ineach of said third windings and allow an output signal to appear only ifa given plurality of said third windings each concurrently develop agiven potential.

3. An electrical circuit comprising a plurality of signal sourcesincluding at least one complementary source; a transformer for each ofsaid sources, each transformer having a primary connected to itscomplementary source; each transformer having a secondary; an outputcircuit interconnecting said secondaries for producing an output signalevent a given plurality of said secondaries have potentials inducedtherein concurrently, said output circuit including a source of biasconnected to the output for preventing appearance of an output signal inevent less than said predetermined number of secondaries concurrentlydeveloped potentials induced therein, and means for limiting thepotential induced in each of said secondaries.

4. An electrical circuit comprising a plurality of signal sourcesincluding at least one complementary source a transformer for each ofsaid sources; each transformer having a primary connected to itscomplementary signal source and a secondary, an impedance means inseries with each secondary, each impedance means and its secondaryforming a branch circuit, means connecting said branch circuits inparallel with each other, and output means including a load and a sourceof bias connected to said branch circuits for surpassing current flowfrom said branch circuits to said load until the sum of the currents insaid branch circuits exceeds a predetermined minimum established by saidsource of bias.

5. An electrical circuit as dened in claim 4 including a limiterconnected to each branch circuit to limit the current iiow therein andthereby limit the magnitude of the contribution of each branch circuitto the sum of the currents from the branch circuits.

6. A gate for an electrical circuit comprising a plurality of magneticamplifiers having cores characterized by substantially rectangularhysteresis loops, each of said amplifiers having a power winding, thepower windings being connected in parrallel with each other, a source ofpower pulses tending to pass current through the parallel connectedpower windings, a load in series with said source and said parallelwindings, means for biasing the load so that it is energized by saidpulses only when at least a predetermined current flows through saidparallel power windings, a control winding on each core, and means forselectively energizing the control windings during the spaces betweenpulses to thereby condition the cores to allow current flow through eachof said parallel power windings from said source of power in dependenceupon the energization of the corresponding control winding theresistances of the parallel circuits including said windings being sorelated to each other and t0 Said biasing means that only when saidpredetermined current flow through said parallel power windings isenergy fed to said load.

7. A gating circuit comprising a source of pulse energy, a load, meansfor gating the flow of energy from said source to said load including aplurality of transformers respectively having secondary windingsconnected together in series so that a predetermined plurality thereofmust have predetermined potentials across the same in order to deliver acumulative given potential to the load, and a plurality of voltagelimiters each respectively connected to an associated one of saidsecondary windings to oppose their respective potentials and therebylimit their contributions to the energy flowing to said load.

8. In a computer circuit, a plurality of signal circuits carrying pulsesrepresenting binary numbers, a saturable core for each circuit, awinding on each core connected to its complementary signal source forresetting the core in response to each signal pulse, pulse generatormeans for generating a train of spaced pulses, the signal pulsesoccurring during spaces between pulses of the pulse generator, a primarywinding on each core energized by said pulse generator means forperiodically setting those of said cores previously reset by signalpulses, a secondary winding on each core, said secondary windings eachhaving a potential produced therein in response to said spaced pulsesand a series circuit including said secondary windings and alsoincluding a rectifier, a driven circuit and a source of potential biasof magnitude greater than the potential induced in any one of saidsecondary windings, said source of bias and the rectifier being seriallyconnected and having such polarities that current will iiow to saiddriven circuit only if the sum of the potentials developed in saidsecondaries exceed the potential of the source of bias.

9. A gate for an electrical circuit comprising a source of pulses, aplurality of magnetic ampliiers having cores characterized bysubstantially rectangular hysteresis loops, each of said amplifiershaving a power winding, the power windings being shunted across eachother, a source of power pulses tending to pass current through theshunted power windings, a load in series with said source, means forbiasing the load so that it is energized by said pulses only when atleast a predetermined current iiows through the shunted windings, acontrol winding on each core, means for selectively energizing thecontrol windings during the spaces between pulses to condition the coresfor the time when pulse energy is impressed on the power windings, theresistances of the circuits including said windings being so related toeach other and to said biasing means that a predetermined number of saidmagnetic amplifiers must pass current through said shunted windingsbefore pulse energy from said source will be fed to said load, andrectifier means in series with each power winding.

10. A gate for an electrical circuit as defined in claim 9 having alimiter connected to each. secondary winding to limit the magnitude ofits contribution to the load.

1i. In combination, at least three saturable cores, means for applyingspaced pulses o magnetizing forces to said cores, input means associatedwith each core for reverting the core during the spaces between pulsesin response to predetermined input conditions, at least first, secondand third coils on each core, iirst, second, third and fourth loads,means connecting the first coils of each core to the iirst load andincluding means to energize the iirst load only if all three of saidirstpcoils have predetermined potentials concurrently induced in them,means connecting the second coils of the first and second cores to thesecond load and including -means to energize the second load only itboth the coils connected thereto have predetermined potentialsconcurrently induced therein, means connecting the third coils of thesecond and third cores to the third load and including means to energizethe third load only if both the coils connected thereto havepredetermined potentials concurrently induced therein, and meansconnecting the third coil of the first core and the second coil of thethird core to the fourth load and including means to energize the fourthload only if both the coils connected thereto have predeterminedpotentials concurrently induced therein.

12. The combination of claim 11 including means associated with eachcore for limiting the potentials induced in the coils.

13. The combination of claim l2 in which the lastnamed means includesall the following: a coil for the core, a rectifier, a source of directcurrent potential, said coil, rectifier and source being connected inseries with the source so that said rectier is back-biased unless thepotential induced in said coil exceeds the potential of said source.

14. In a half-adder rst and second saturable cores, means for applyingspaced pulses of magnetizing force to the cores which will drive them tosaturation unless the cores are reverted during the spaces betweenpulses, irst input means for the first core to revert the core during aspace between pulses in response to a predetermined lcondition at thefirst input means, second input means for the second core to revert thecore during a space between pulses in response to a predeterminedcondition at the second input means, three coils on each core, a sumoutput, means connecting the first coils on the cores in series witheach other to give a resultant signal at the sum output when there is aux change in the first core in the absence of a ilux change in thesecond with the potentials yof these coils cancelling each other whenthere is a rtiux change in both cores, means connecting the Second coilson the cores in series with each other to give a resultant signal at-thesum output when there is a llux change in the second core in the absenceof a liux change in the irst core, a carry output, and means connectingthe third coils on the cores in series with each other and with thecarry output and including bias means for cancelling the potentialinduced in the carry output circuit unless potential is induced in bothof the coils of that circuit.

l5. In a half-adder first and second saturable cores, n

means :tor applying spaced pulses of magnetizing force to the coreswhich will drive them to saturation unless the cores are reverted duringthe spaces between pulses, iirst input means for the tirst core torevert the core during a space between pulses in response to apredetermined condition at the irst input means, second input means Jforthe second core to revert the core during arspacebetween pulses inresponse to a predetermined condition at the second input means, threecoils on each core,fa sum output, means connecting the first coils onthe cores in series with each other to give a resultant signal at thesum output when there is a linx change in the first core in the absenceof a iiux change in the second with the potentials of these coils,cancelling each other when there is a flux change in both cores, meansconnecting the second coils on the cores in series with each other togive a resultant signal at the sum output when there is a flux change inthe second core in the absence of a flux change in the irst core, acarry output, means connecting the third coils on the cores in serieswith each other and with the carry output and including bias means forcancelling the potential induced in the carry output circuit unlesspotential is induced in both of the coils of that circuit, and means forlimiting the potential induced in at least one of the coils on one ofthe cores.

16. In a half-adder first and second saturable cores, means for applyingspaced pulses of magnetizing force to the cores which will drive them tosaturation unless the cores are reverted during the spaces betweenpulses, first input means for the first core to revert the core during aspace between pulses in response to a predetermined condition at thefirst input means, second input means for the second core to revert thecore during a space between pulses in response to a predeterminedcondition at the second input means, three coils on each core, a sumoutput, means connecting the iirst coils on the cores in series witheach other to give a resultant signal at the sum output when there is afiux change in the first core in the absence of a flux change in thesecond with the potentials of these coils cancelling each other whenthere is a flux change in both cores, means connecting the second coilson the cores in series with each other to give a resultant signal at thesum output when there is a iiuX change in the second core in the absenceof a liux change in the first core, a carry output, means connecting thethird coils on the cores in series with each other and with the carryoutput and including bias means for cancelling the potential induced inthe carry output circuit unless potential is induced in both of thecoils of that circuit, and means for limiting Ithe potentials induced insaid first and second coils on the two cores.

1,7. A half-adder as defined in claim 16 in which the last-named meansincludes all the following: a coil on one of the cores, a rectifier, asource of potential, and means connecting the coil, source and rectifierin series to limit the tiux change in the core.

l8, A half-adder as defined in claim 17 including rectii fier meansconnecting the third coil on the other core in series with said biasmeans to limit the iiux change in the second core.

19. A half-adder as defined in claim l6 in which the last-named meanscomprises a rectifier and a source of potential connected to the sumoutput to act as a limiter so that the circuit will tend to limit therate of fiux change in the first and second coils of either core when itis alone operating on an unsaturated portion of its hysteresis loop.

20. A half-adder as dened in claim 19 including a limiter connected ytothe carry output to limit the potential thereof to a predeterminedmaximum and thereby limit the rate of fiux change in the cores when bothare operating simultaneously on unsaturated portions of their hysteresisloops.

21. A gate for an electrical circuit comprising a load; a plurality oimagnetic amplifiers, each of said amplifiers including a corecharacterized by a substantially rectangular hysteresis loop, a primarywinding on each core, a secondary winding on each core; means forenergizing said primary windings with pulses; said secondary windingsbeing in a series circuit with the load and with each other andconnected so that the potentials induced in said windings in response tosaid pulses are in additive relation to each other, a primary winding oneach core; a control winding on each core; means tor selectivelyenergizing said control windings in the time between pulses toselectively condition said cores so that said secondary windings havepotentials induced by the energization of said primary windings on thoseof said cores having previously energized control windings; a source offixed bias potential and a rectifier in series circuit with each otherand with said load, said bias potential and said rectifier being or"such polarity and magnitude that potentials induced in a given pluralityof said secondaries are needed to produce current through said rectifierand said load.

22. A gate as defined in claim 21 includes a means for limiting thepotential across each one of said secondary windings.

23. A magnetic gating system comprising a plurality of magnetic coreseach having a substantially rectangular hysteresis characteristic withpositive and negative remanent states, a iirst winding linking each corefor selectiveiy magnetizing the core to the positive remanent state inresponse to input signals applied to said first winding during certainalternate time periods, a second winding linking each core, a source ofperiodic power pulses coupled to said second windings for concurrentlymagnetizing the cores to the negative remanent state during time periodsintermediate said certain periods of said input signals, a third windinglinking each core for producing a potential in response to a change inthe magnetization of the core from one remanent state to another, meansfor connecting said third windings in series, a unilateral conductingelement interposed in series with said third windings and poled to passcurrents induced by said periodic power pulses, a potential sourceconnected in series with said series connected third windings and saidunilateral conducting element for providing a fixed bias potential ofmagnitude and polarity to prevent current flow through said unilateralconducting element unless said series connected third windings produce atotal potential greater than the bias potential in response to apredetermined plurality of said cores having been magnetized to thepositive remanent state by input signals prior to the energization ofsaid second windings by said power pulses, and potential limiting meansfor establishing a maximum potential which can be produced across one ofsaid third windings.

24. A magnetic gating system comprising a plurality of magnetic coreseach being substantially saturated at positive and negative remanence, asignal winding linking each of said cores for magnetizing thecorresponding core to positive remanence in response to a signal input,a power winding linking each of said cores, a source of power pulsescoupled to said power windings for concurrently magnetizing said coresto negative remanence during a period fol-lowing the application of saidsignal inputs, an output winding on each core for developing a potentialtherein in response `to the application of said power pulses to saidpower windings on those of said cores previously magnetized to positiveremanence, a load, means coupling said output winding in series witheach other and said load in polarity to provide additive relationshipbetween the potentials of all said output windings in response to saidpower pulses, a first rectifier means interposed between adjacent outputwindings and poled to permit current fiow only in response to potentialsproduced in those of said output windings linking cores previouslymagnetized to positive remanence by input signals to correspondingsignal windings, a fixed potential bias interposed in series with saidoutput windings, said first rectifier means and said load during saidpower pulses for preventing current ow in said load except upon theconcurrent development of potentials in a predetermined plurality o'rsaid load windings in response to said power pulses, potential iimitingmeans including a second rectifier means each shunting selected outputwindings for limiting the maximum potential developed by thecorresponding output windings.

25. ln an electrical circuit; a plurality of sources of signal pulses;and means responsive to signal pulses from said sources to produce anoutput only in response to signal pulses from at least a predeterminedplurality of said sources, said responsive means comprising a core foreach of said sources, winding means linking each of said cores toselectively alter the magnetization of each of said cores in response toa signal from a corresponding source, potential developing meansincluding a second winding on each of said cores responsive to themagnetization of said cores by said winding means for developing thereinpotentials of predetermined magnitude, means including both a load and asource of bias for producing current flow through said load when thepotential developed by said potential developing means exceeds thepotential of said source of bias, rectifier means for limiting currentflow in said second windings to a single direction, and limiting meansincluding a source of potential in circuit with said second windings forlimiting the individual effect of each of said second winding upon thedevelopment of the potential of said potential developing means.

26. A gate for an electrical circuit comprising la source of pulses, apiurality of magnetic amplifiers, each of said amplifiers having a corecharacterized by a substantially rectangular hysteresis loop, a powerwinding linking each of said cores, the power windings being connectedin parallel with each other, a source of spaced power pulses tending topass current through the parallel connected power windings, a load inseries with said source and said parallel power windings, means forbiasing the load so that it is energized by said pulses only when atleast a predetermined current fiows through said parallel powerwindings, said last-named means including a source of potential, animpedance, and a diode connected in series circuit, said series circuitbeing connected to said parallel connected power windings at a pointbetween said diode and said impedance, said bias potential and saiddiode being poled to maintain said intermediate point at a xed potentialin the absence of at least a predetermined current fiow through saidparallel power windings, a control winding on each core, and means forselectively energizing the control windings during the space betweensaid power pulses to thereby condition the cores to selectively allowcurrent flow through each of said parallel power windings from saidsources of power in dependence upon the energization of thecorresponding one of said control windings, an impedance in each of theparallel circuits including said power windings, said impedances beingof magnitude to allow current iow in each of said parallel powerwindings such that only the sum of the currents through a predeterminedplurality of said parallel power windings exceeds the said predeterminedcurrent dow and thereby supplies energy to said load, and potentiallimiting means including a source of potential coupled to said parallelconnected power windings in manner to limit the current through each ofsaid impedances to a predetermined value.

27. A logic circuit comprising a plurality of current paths, each ofsaid paths separately including a signal-responsive switching means forsubstantially cutting olf current ow and for permitting current ilow ofa certain magnitude in response to different input signals, a load, acurrent responsive circuit providing a low impedance path to currentsless than that supplied by a certain plurality of said paths and a highimpedance to currents supplied by said certain plurality of said paths,means connecting said paths in a rst parallel combination, meansconnecting said load and said current responsive circuit in a secondparallel combination, and means connecting said parallel combinations inseries and for applying an operating potential across saidseries-connected parallel combinations, whereby said load issubstantially energized by current through said paths only when saidswitching means permits current ow from said certain plurality of saidpaths.

28. A logic circuit as recited in claim 27 wherein said currentresponsive circuit includes a unilateral conductor, an impedance, `and apotential source connected in a series circuit, the potential of saidpotential source being such as to bias said unilateral conductor in aforward direction to present a low impedance to currents less than thatsupplied by said certain plurality of said paths and to present a highimpedance to current supplied by said certain plurality of said paths,the junction of said unilateral conductor .and said impedance beingconnected to a terminal of said load and to terminals of said currentpaths.

29. A logic circuit as recited in claim 27 including means connected toeach of said paths for limiting the current supplied through each ofsaid paths to a certain magnitude.

30. A logic circuit `comprising a plurality of current paths, each ofsaid current paths separately including an impedance and a switchingmeans for substantially cutting off current flow therethrough inresponse to an input signal of one magnitude and permitting current flowin response to an input signal of another magnitude, a load, a sourceconnected to said current paths tending to produce predeterminedcurrents in said current paths, means connecting said current paths inparallel with each other and in series with said load, and a circuit inparallel with said load and responsive to the total of said currentsthrough said paths to present a low impedance across said load to totalcurrents through said paths substantially below a certain magnitudecorresponding to currents through a plurality of said paths and topresent a high impedance to total currents through said paths above saidcertain magnitude.

31. A logic circuit as recited in claim 30 wherein said switching meansincludes a magnetic core having a substantially rectangular hysteresisloop, a primary winding and a secondary winding on said core, saidprimary winding being linked to said core to set said core in a rstremanent state in response to an input signal of said other magnitude,means connecting said secondary winding in the corresponding one of saidcurrent paths, said secondary winding linking said core so that saidsecondary winding has a minimum impedance to current 110W from saidsource when said core iS sst in said first remanrnt State- 2 32. A logiccircuit as recited in claim 31y including means connected to each ofsaid paths for limiting the magnitude of current therein.

33. A logic circuit comprising a pluralityof sources of signals, a load,separate impedances each connected in n an individual series circuitbetween a terminal of a diterent one of said sources and a firstterminal of said load for producing a predetermined current in each ofsaid series circuits in response to signals from corresponding sources,means connecting a second terminal of said load to another terminal ofeach of said sources of signals, a circuit connected in parallel withsaid load, said parallel circuit including an impedance and a potentialsource in series with said last-named impedance, said potential sourcebeing polcd to produce a current flow through said last-named impedancein a direction corresponding to the direction of current produced bysaid sources in said lastnamed impedance and of magnitude substantiallyequal to the total of said current produced in a certain number of saidseries circuits, and a unilateral conductor connected in parallel withsaid load and poled to present a high impedance to said predeterminedcurrent and a low impedance to current produced by said potential sourcewhereby said parallel circuit effectively forms a low impedance acrosssaid load for the total of said predetermined current in said certainnumber of said series circuits and forms a high impedance across saidload for current in said series circuits in excess of said total.

34. A logic circuit comprising a potential source, a load, a pluralityof parallel current paths connected between said potential source andsaid load, said current paths each including an impedance and a signalresponsive switching means in series with said impedance for effectivelycompleting and interrupting said current paths selectively in responseto corresponding signals of first and second values, said potentialsource and said path impedances bcing of magnitude to produce a certaintotal current through a certain plurality of said current paths inresponse to completion of said certain plurality of said current pathsby said switching means, and a current responsive circuit connected inparallel to said load, said current responsive circuit having a loweffective impedance for said certain total current in said paths and ahigh effective impedance for a total current in said paths greater thansaid certain total current.

References Cited in the le of this patent UNITED STATES PATENTS2,591,406 Carter Apr. l, 1952 2,666,151 Rajchman et al Jan. 12, 19542,685,644 Toulon Aug. 3, 1954 2,695,993 Haynes Nov. 30, 1954 2,696,347Lo Dec. 7, 1954 2,741,757 Devel et al Apr. 1G, 1956 2,741,758 Cray Apr.10, 1956 2,776,380 Andrews ian. 1, 1957 2,806,648 Rutledge Sept, 17,1957 OTHER REFERENCES Olsen: A Magnetic-Matrix Switch and ItsIncorporation into a Coincident-Current Memory, M. I. T. Master ofScience Thesis, June 6, 1952.

Newhouse: A Review of Magnetic and Ferro-Electric Computing Components,Electronic Engineering, May 1954, pp. l92-199.

Brean: Magnetic Matrix Switch Reads Binary Output, Electronics, May1954, pp. 157-159,

26. A GATE FOR AN ELECTRICAL CIRCUIT COMPRISING A SOURCE OF PULSES, APLURALITY OF MAGNETIC AMPLIFIERS, EACH OF SAID AMPLIFIERS HAVING A CORECHARACTERIZED BY A SUBSTANTIALLY RECTANGULAR HYSTERESIS LOOP, A POWERWINDING LINKING EACH OF SAID CORES, THE POWER WINDINGS BEING CONNECTEDIN PARALLEL WITH EACH OTHER, A SOURCE OF SPACED POWER PULSES TENDING TOPASS CURRENT THROUGH THE PARALLEL CONNECTED POWER WINDINGS, A LOAD INSERIES WITH SAID SOURCE AND SAID PARALLEL POWER WINDINGS, MEANS FORBIASING THE LOAD SO THAT IT IS ENERGIZED BY SAID PULSES ONLY WHEN ATLEAST A PREDETERMINED CURRENT FLOWS THROUGH SAID PARALLEL POWERWINDINGS, SAID LAST-NAMED MEANS INCLUDING A SOURCE OF POTENTIAL, ANIMPEDANCE, AND A DIODE CONNECTED IN SERIES CIRCUIT, SAID SERIES CIRCUITBEING CONNECTED TO SAID PARALLEL CONNECTED POWER WINDINGS AT A POINTBETWEEN SAID DIODE AND SAID IMPEDANCE, SAID BIAS POTENTIAL AND SAIDDIODE BEING POLED TO MAINTAIN SAID INTERMEDIATE POINT AT A FIXEDPOTENTIAL IN THE ABSENCE OF AT LEAST A PREDETERMINED CURRENT FLOWTHROUGH SAID PARALLEL POWER WINDINGS, A CONTROL WINDING ON EACH CORE,AND MEANS FOR SELECTIVELY ENERGIZING THE CONTROL WINDINGS DURING THESPACE BETWEEN SAID POWER PULSES TO THEREBY CONDITION THE CORES TOSELECTIVELY ALLOW CURRENT FLOW THROUGH EACH OF SAID PARALLEL POWERWINDINGS FROM SAID SOURCES OF POWER IN DEPENDENCE UPON THE ENERGIZATIONOF THE CORRESPONDING ONE OF SAID CONTROL WINDINGS, AN IMPEDANCE IN EACHOF THE PARALLEL CIRCUITS INCLUDING SAID POWER WINDINGS, SAID IMPEDANCESBEING OF MAGNITUDE TO ALLOW CURRENT FLOW IN EACH OF SAID PARALLEL POWERWINDINGS SUCH THAT ONLY THE SUM OF THE CURRENTS THROUGH A PREDETERMINEDPLURALITY OF SAID PARALLEL POWER WINDINGS EXCEEDS THE SAID PREDETERMINEDCURRENT FLOW AND THEREBY SUPPLIES ENERGY TO SAID LOAD, AND POTENTIALLIMITING MEANS INCLUDING A SOURCE OF POTENTIAL COUPLED TO SAID PARALLELCONNECTED POWER WINDINGS IN MANNER TO LIMIT THE CURRENT THROUGH EACH OFSAID IMPEDANCES TO A PREDETERMINED VALUE.